1. Field of the Invention
This invention relates to differential amplifier circuits, and more particularly to differential amplifier circuits employing junction field effect transistors (JFETs) as the differential sensing elements.
2. Description of the Prior Art
It is generally desirable to reduce input bias currents in numerous types of electrical circuits. In differential amplifiers which employ JFETs as the differential elements, input bias currents may be attributed to four principal factors:
(1) impact ionization currents resulting from avalanche multiplication;
(2) generation currents formed within the space charge region due to generation-recombination centers;
(3) epitaxial-to-substrate junction leakage currents, for circuits in which junction isolation rather than dielectric isolation is used; and
(4) diffusion currents resulting from electron-hole pairs generated outside of the space charge region diffusing into the space charge region.
Efforts to reduce the input bias current have generally focused on reducing the epitaxial-substrate junction leakage current by the introduction of various compensating currents. These efforts have not addressed the effect of impact ionization current, which can be quite significant when the JFETs are operated at high currents and with large gate-drain voltages.
It is normally desirable to operate the JFETs in the saturated region, at which they exhibit a high output impedance. Saturation is reached when the gate-drain voltage exceeds the device's pinchoff voltage (V.sub.p). In this mode a region of the JFET channel is pinched off, and the drain current that continues to flow is substantially independent of variations in the gate-drain voltage. In order to assure that the JFETs remain saturated, their gate-drain voltages may be held at a level much greater than V.sub.p, thereby substantially increasing the impact ionization current contribution to input bias current.